/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

#ifndef _NTHW_FPGA_REG_DEFS_MAC_RX_
#define _NTHW_FPGA_REG_DEFS_MAC_RX_

/* MAC_RX */
#define MAC_RX_BAD_FCS (0xca07f618UL)
#define MAC_RX_BAD_FCS_COUNT (0x11d5ba0eUL)
#define MAC_RX_FRAGMENT (0x5363b736UL)
#define MAC_RX_FRAGMENT_COUNT (0xf664c9aUL)
#define MAC_RX_PACKET_BAD_FCS (0x4cb8b34cUL)
#define MAC_RX_PACKET_BAD_FCS_COUNT (0xb6701e28UL)
#define MAC_RX_PACKET_SMALL (0xed318a65UL)
#define MAC_RX_PACKET_SMALL_COUNT (0x72095ec7UL)
#define MAC_RX_TOTAL_BYTES (0x831313e2UL)
#define MAC_RX_TOTAL_BYTES_COUNT (0xe5d8be59UL)
#define MAC_RX_TOTAL_GOOD_BYTES (0x912c2d1cUL)
#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (0x63bb5f3eUL)
#define MAC_RX_TOTAL_GOOD_PACKETS (0xfbb4f497UL)
#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (0xae9d21b0UL)
#define MAC_RX_TOTAL_PACKETS (0xb0ea3730UL)
#define MAC_RX_TOTAL_PACKETS_COUNT (0x532c885dUL)
#define MAC_RX_UNDERSIZE (0xb6fa4bdbUL)
#define MAC_RX_UNDERSIZE_COUNT (0x471945ffUL)

#endif	/* _NTHW_FPGA_REG_DEFS_MAC_RX_ */
